A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist - 2015
This transient presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with freelance single-ended browse bitline and write bitline (WBL) and cross-purpose information-aware write structure to facilitate sturdy subthreshold operation and bit-interleaving design for enhanced soft error immunity. The look employs a variation-tolerant line-up write-assist theme where the timing of areaefficient boosted write wordline and negative WBL are aligned and triggered/initiated by the identical low-going global WBL to maximize the write-ability enhancement. A 72-kb check chip is implemented in United Microelectronics Corp. forty-nm low-power (40LP) CMOS. Full functionality is achieved for VDD starting from one.5 to 0.32 V while not redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at one.one V (0.32 V) and 25 °C. At zero.325 V and 25 °C, the chip operates at 600 kHz with five.78 µW total power and 4.69 µW leakage power, providing two× frequency improvement compared with three hundred kHz of our previous seventy two-kb 9T subthreshold SRAM design in the identical 40LP technology. The energy potency (power/frequency/IO) at zero.325 V and 25 °C is zero.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/little bit of our previous design.
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