Design of high speed ternary full adder and threeinput XOR circuits using CNTFETs - 2015


This project proposes a new high speed ternary full adder (TFA) cell for carbon nano tube field effect transistor (CNTFET) technology. The proposed design has a symmetric pull-up and pull-down networks along with a resistive voltage divider as its integral half, which is configured using transistors. The design takes inputs through a decoding unit and uses ternary nature of A & B however inherent binary nature of Cin resulting in simplicity in design. The design demonstrates high driving power and robustness in terms of insusceptibility to voltage and temperature variations. The sum generation unit of proposed design is any changed for achieving an energy efficient 3-input ternary XOR circuit which will be used as a basic cell in modern circuit style. Hspice simulation results with 32nm Stanford CNTFET model show 49p.c reduction in delay with nineteen% progress in power-delay product (PDP) for the proposed TFA and 43% reduction in delay with 48 percent improvement in PDP for the proposed 3 input ternary XOR circuit compared with the CNTFET-primarily based styles, recently revealed within the literature.

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