PROJECT TITLE:

Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing - 2015

ABSTRACT:

Speed and the performance of any digital signal processor are largely determined by the efficiency of the multiplier units gift among. The use of Vedic mathematics has resulted in vital improvement within the performance of multiplier architectures used for top speed computing. This project proposes 4-bit and eight-bit multiplier architectures primarily based on Urdhva Tiryakbhyam sutra. These low power designs are realized in forty five nm CMOS Method technology using Cadence EDA tool.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE : Underwater Ultrasonic Wireless Power Transfer: A Battery-Less Platform for the Internet of Underwater Things ABSTRACT: New maritime applications, including scientific research and business ventures, will be made
PROJECT TITLE : Industrial Power Load Forecasting Method Based on Reinforcement Learning and PSO-LSSVM ABSTRACT: It is very difficult to obtain high-performance industrial power load forecasting as a result of the many different
PROJECT TITLE : Blockchain Power Trading and Energy Management Platform ABSTRACT: The purpose of this research was to develop a vehicle-to-everything blockchain power trading and energy management platform. The platform was
PROJECT TITLE : Optimal Phase Shift Control to Minimize Reactive Power for a Dual Active Bridge DC-DC Converter ABSTRACT: Under non-unity voltage gain conditions, modulating the phase shift ratios in a dual active bridge (DAB)
PROJECT TITLE : Modular Parallel Multi-Inverter System for High-Power Inductive Power Transfer ABSTRACT: An inverter-based parallel multi-inverter system is proposed to deliver high and extendable power levels for inductive

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry