Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication - 2016


This paper proposes a straightforward and efficient Montgomery multiplication algorithm such that the low-price and high-performance Montgomery modular multiplier will be implemented accordingly. The proposed multiplier receives and outputs the information with binary illustration and uses solely one-level carry-save adder (CSA) to avoid the carry propagation at every addition operation. This CSA is also used to perform operand precomputation and format conversion from the carry-save format to the binary representation, leading to an occasional hardware value and short essential path delay at the expense of additional clock cycles for completing one modular multiplication. To beat the weakness, a configurable CSA (CCSA), which could be one full-adder or two serial half-adders, is proposed to cut back the additional clock cycles for operand precomputation and format conversion by 0.5. Additionally, a mechanism that can detect and skip the unnecessary carry-save addition operations within the one-level CCSA design while maintaining the short vital path delay is developed. Thence, the additional clock cycles for operand precomputation and format conversion will be hidden and high throughput will be obtained. Experimental results show that the proposed Montgomery modular multiplier will achieve higher performance and important space-time product improvement compared with previous styles.

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