Digital Arithmetic

No	Project Titles	Abstract
1 .	Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach - 2016	Abstract
2 .	MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016	Abstract
3 .	A Modified Partial Product Generator for Redundant Binary Multipliers - 2016	Abstract
4 .	Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication - 2016	Abstract
5 .	An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016	Abstract
6 .	Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing - 2016	Abstract
7 .	A Mixed-Decimation MDF Architecturefor Radix-2k Parallel FFT - 2016	Abstract
8 .	Design of Efficient BCD Adders in Quantum Dot Cellular Automata - 2016	Abstract
9 .	PNS-FCR: Flexible Charge RecyclingDynamic Circuit Technique forLow-Power Microprocessors - 2016	Abstract

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