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Adders

No Project Titles Abstract
1 . Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design - 2016 Abstract
2 . MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016 Abstract
3 . Multi Precision Arithmetic Adders - 2016 Abstract
4 . Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit - 2016 Abstract
5 . Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest - 2016 Abstract
6 . High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2016 Abstract
7 . Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding - 2016 Abstract
8 . Floating-Point Butterfly Architecture Based on Binary SignedDigit Representation - 2016 Abstract
9 . Design and Analysis of Inexact Floating-Point Adders - 2016 Abstract
10 . Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication - 2016 Abstract
11 . Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range - 2016 Abstract
12 . Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding - 2016 Abstract
13 . Design of adder and subtractor circuits in majority logic-based field-coupled QCA Nano computing - 2016 Abstract
14 . Design of Efficient BCD Adders in Quantum Dot Cellular Automata - 2016 Abstract
15 . Analysis of 8 bit RCA adder at different nanometer regime - 2016 Abstract

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