Logic Design

No Project Titles Abstract
1 . Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs - 2016 Abstract
2 . MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016 Abstract
3 . High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2016 Abstract
4 . Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m) - 2016 Abstract
5 . A Modified Partial Product Generator for Redundant Binary Multipliers - 2016 Abstract
6 . Hybrid LUT/Multiplexer FPGA Logic Architectures - 2016 Abstract
7 . Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication - 2016 Abstract
8 . High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier - 2016 Abstract
9 . A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory - 2016 Abstract
10 . Knowledge-Based Neural Network Model for FPGA Logical Architecture Development - 2016 Abstract
11 . An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016 Abstract
12 . Digital Multiplierless Realization of Two-CoupledBiological Hindmarsh–Rose Neuron Model - 2016 Abstract
13 . Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016 Abstract
14 . Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers - 2016 Abstract
15 . Design for Testability of Sleep Convention Logic - 2016 Abstract
16 . A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2016 Abstract
17 . A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones - 2016 Abstract
18 . A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register - 2016 Abstract
19 . A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography - 2016 Abstract
20 . Design of adder and subtractor circuits in majority logic-based field-coupled QCA Nano computing - 2016 Abstract
21 . Design of Efficient BCD Adders in Quantum Dot Cellular Automata - 2016 Abstract
22 . PNS-FCR: Flexible Charge RecyclingDynamic Circuit Technique forLow-Power Microprocessors - 2016 Abstract
23 . Low-Power Variation-Tolerant Nonvolatile Lookup Table Design - 2016 Abstract

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