Design and Analysis of Inexact Floating-Point Adders - 2016


Power has become a key constraint in nanoscale integrated circuit style because of the increasing demands for mobile computing and higher integration density. As an emerging computational paradigm, an inexact circuit offers a promising approach to considerably reduce both dynamic and static power dissipation for error-tolerant applications. During this paper, an inexact floating-point adder is proposed by approximately planning a lover subtractor and mantissa adder. Related operations such as normalization and rounding also are dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact style; it shows that the inexact floating-purpose adder design depends on the applying knowledge vary. High dynamic vary images are then processed using the proposed inexact floating-purpose adders to show the validity of the inexact style; comparison results show that the proposed inexact floating-point adders can improve the facility consumption and power-delay product by 29.ninety eight and 39.sixty percent, respectively.

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