High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier - 2016 PROJECT TITLE : High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier - 2016 ABSTRACT: The Serial-out bit-level multiplication theme is characterized by an necessary latency feature. It's a capability to sequentially generate an output bit of the multiplication end in each clock cycle. But, the computational complexity of the present serial-out bit-level multipliers in GF(2m) using traditional basis illustration, limits its usefulness in several applications; hence, an optimized serial-out bit-level multiplier using polynomial basis representation is needed. During this paper, we tend to propose new serial-out bit-level Mastrovito multiplier schemes. We show that in terms of the time complexities, the proposed multiplier schemes outperform the existing serial-out bit-level schemes out there within the literature. Additionally, using the proposed multiplier schemes, we gift new hybrid-double multiplication architectures. To the simplest of our information, this is the primary time such a hybrid multiplier structure using the polynomial basis is proposed. Prototypes of the presented serial-out bit-level schemes and the proposed hybrid-double multiplication architectures (10 schemes in total) are implemented over both GF(2163) and GF(2233), and experimental results are presented. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Computational Complexity Logic Design Polynomials Multiplying Circuits Circuit Optimisation Serial-Out Polynomial Basis Bit-Level Multiplier Mastrovito Multiplier Hybrid-Double Multiplication Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication - 2016 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding - 2016
