PROJECT TITLE :

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2016

ABSTRACT:

During this paper, we have a tendency to present a carry skip adder (CSKA) structure that has a higher speed nevertheless lower energy consumption compared with the standard one. The speed enhancement is achieved by applying concatenation and incrementation schemes to enhance the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with each mounted stage size and variable stage size styles, wherein the latter more improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, that lowers the facility consumption while not significantly impacting the speed, is presented. This extension utilizes a changed parallel structure for increasing the slack time, and hence, enabling more voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of different adders employing a 45-nm static CMOS technology for a wide selection of offer voltages. The results that are obtained using HSPICE simulations reveal, on average, forty fourp.c and 38percent enhancements within the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the ability-delay product was the lowest among the structures thought-about during this paper, while its energy-delay product was nearly the identical as that of the Kogge-Stone parallel prefix adder with significantly smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the ability consumption compared with the latest works during this field while having a fairly high speed.


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