PROJECT TITLE :

Train Time Delay Prediction for High-Speed Train Dispatching Based on Spatio-Temporal Graph Convolutional Network

ABSTRACT:

Train delay prediction has the potential to improve the quality of train dispatching, which in turn enables the dispatcher to more accurately estimate the running state of the train and come to a decision that is reasonable regarding train dispatching. A single train's delay can be caused by a number of different things, including the volume of passengers, a problem, severe weather, or an improper dispatching strategy. The exact time that a train will pull out of a station is typically decided by dispatchers, whose abilities are constrained by the strategies and information at their disposal. The currently available methods for predicting train delays are unable to take into account, in a comprehensive manner, the temporal and spatial dependence that exists between the multiple trains and routes. In this paper, rather than attempting to forecast the specific amount of time that any given train will be delayed, our focus is on forecasting the overall cumulative effect of train delays over a given time period. This effect is represented by the total number of delayed arrivals at any given station. To predict the collective cumulative effect of train delay in one station for the purposes of train dispatching and emergency planning, we propose a Deep Learning framework called the train spatio-temporal graph convolutional network (TSTGCN). The recent, daily, and weekly components are the primary building blocks of the model that has been proposed. Each component includes a spatio-temporal attention mechanism and a spatio-temporal convolution, both of which are able to effectively capture spatio-temporal qualities. The final result of the prediction is determined by the weighted fusion of the three different components. The experiments conducted on the train operation data obtained from the China Railway Passenger Ticket System reveal that TSTGCN performs noticeably better than the existing advanced baselines when it comes to the prediction of train delays.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE : Harmonic Loss Reduction in High Speed Motor Drive Systems by Flying Capacitor Multilevel Inverter ABSTRACT: When inverters drive an AC motor, the harmonic components of the output voltage result in extra iron
PROJECT TITLE :A Low-Power High-Speed Comparator for Precise Applications - 2018ABSTRACT:A coffee-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator furthermore as the latch
PROJECT TITLE :A Low-Power Yet High-Speed Configurable Adder for Approximate Computing - 2018ABSTRACT:Approximate computing is an efficient approach for error-tolerant applications as a result of it will trade off accuracy for
PROJECT TITLE :A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design - 2018ABSTRACT:Multiplication may be a key elementary perform for several error-tolerant applications. Approximate multiplication is taken
PROJECT TITLE :Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit - 2017ABSTRACT:In this paper, a hybrid one-bit full adder design using both complementary metal-oxide-semiconductor (CMOS) logic and

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry