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1 |
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling - 2016 |
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2 |
A Comparator-Based Rail Clamp - 2016 |
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3 |
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply - 2016 |
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4 |
A High Throughput List Decoder Architecturefor Polar Codes - 2016 |
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5 |
A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones - 2016 |
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6 |
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier - 2016 |
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7 |
Design and simulation of Turbo encoder in quantum-dot cellular automata - 2016 |
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8 |
Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design - 2016 |
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9 |
Graph-Based Transistor Network GenerationMethod for Super gate Design - 2016 |
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10 |
High-Performance NB-LDPC Decoder With Reduction of Message Exchange - 2016 |
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11 |
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2016 |
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12 |
Low-Power ASK Detector for Low ModulationIndexes and Rail-to-Rail Input Range - 2016 |
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13 |
Low-Power FPGA Design Using Memorization-Based Approximate Computing - 2016 |
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14 |
Speculative Look ahead for Energy-Efficient Microprocessors - 2016 |
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15 |
USE: A Universal, Scalable and Efficient clocking scheme for QCA - 2016 |
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16 |
VLSI Design for Convolutive BlindSource Separation - 2016 |
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17 |
Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit - 2016 |
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