Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios - 2016

PROJECT TITLE :

Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios - 2016

ABSTRACT:

Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an very powerful task. Wireless standards like wireless native space network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the prevalence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is kind of advanced. During this study, the authors propose a coffee complexity and space economical reconfigurable architecture for multimode interleaver address generator to support multiple wireless standards. Additionally, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and sixty four-QAM modulation schemes underneath all possible code rates. The reconfigurable address generator for numerous block size and modulation theme are implemented on Xilinx Spartan XC3S40zero FPGA and the functionalities are verified through simulation. The synthesis results of the proposed style shows a discount of 60% in resource utilisation and an improvement of 46p.c in operating frequency over the prevailing approaches.

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