Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016


Radiation-induced multiple bit upsets (MBUs) are a serious reliability concern in nanoscale technology nodes. Occurrence of such errors within the configuration frames of a field-programmable gate array (FPGA) device permanently affects the functionality of the mapped design. Periodic configuration scrubbing combined with an occasional-price error correction theme is an economical approach to avoid such a permanent impact. Existing techniques employ error correction codes with considerably high overhead to mitigate MBUs in configuration frames. During this paper, we present a low-cost error-detection code to detect MBUs in configuration frames also a generic scrubbing scheme to reconstruct the erroneous configuration frame based mostly on the concept of erasure codes. The proposed theme will not need any modification to the FPGA design. Implementation of the proposed theme on a Xilinx Virtex-half dozen FPGA device shows that the proposed theme can detect a hundred% of MBUs within the configuration frames with solely three.3% resource occupation, while the recovery time is comparable with the previous schemes.

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