A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits - 2016 PROJECT TITLE : A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits - 2016 ABSTRACT: Single error correction (SEC) codes are widely used to protect information stored in recollections and registers. In some applications, such as NetWorking, some management bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the info and the associated management bits. It is enticing for these codes to produce quick decoding of the control bits, as these are used to determine the processing of the info and are commonly on the crucial timing path. In this transient, a method to extend SEC codes to support a few extra control bits is presented. The derived codes support quick decoding of the additional management bits and are thus appropriate for NetWorking applications. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Networking Applications Single Error Correction Codes SEC Code Design Fast Decoding Critical Bits Control Bits Critical Timing Path Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers - 2016
