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Field Programmable Gate Arrays

No Project Titles Abstract
1 . An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016 Abstract
2 . Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs - 2016 Abstract
3 . MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016 Abstract
4 . Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios - 2016 Abstract
5 . Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m) - 2016 Abstract
6 . Hybrid LUT/Multiplexer FPGA Logic Architectures - 2016 Abstract
7 . A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory - 2016 Abstract
8 . Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application - 2016 Abstract
9 . Speculative Look ahead for Energy-Efficient Microprocessors - 2016 Abstract
10 . Knowledge-Based Neural Network Model for FPGA Logical Architecture Development - 2016 Abstract
11 . Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching - 2016 Abstract
12 . A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic - 2016 Abstract
13 . An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016 Abstract
14 . High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver - 2016 Abstract
15 . Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 Abstract
16 . A New XOR-Free Approach for Implementation of Convolutional Encoder - 2016 Abstract
17 . Digital Multiplierless Realization of Two-CoupledBiological Hindmarsh–Rose Neuron Model - 2016 Abstract
18 . Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016 Abstract
19 . A Cellular Network Architecture WithPolynomial Weight Functions - 2016 Abstract
20 . Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems - 2016 Abstract
21 . A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2016 Abstract
22 . Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order - 2016 Abstract
23 . A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography - 2016 Abstract
24 . Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016 Abstract
25 . A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation - 2016 Abstract

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