Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division - 2017 PROJECT TITLE :Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division - 2017ABSTRACT:Floating purpose division may be a core arithmetic widely utilized in scientific and engineering applications. This paper proposed an design for double precision floating purpose division. This architecture is intended for twin-mode functionality, which will either compute on a try of double precision operands or on two pairs of single precision operands in parallel. The architecture relies on the series expansion multiplicative methodology of mantissa computation. For this, a completely unique twin-mode Radix-four Changed Booth multiplier is meant, which is employed iteratively within the design of twin-mode mantissa computation. Alternative key parts of floating point division flow (like leading-one-detection, left/right dynamic shifters, rounding, etc.) are also re-designed for the dual-mode operation. The proposed twin-mode architecture is synthesized using UMC 90 nm technology ASIC implementation. Two versions of proposed design are presented, one with single stage multiplier and another with 2 stage multiplier. Compared to a standalone double precision division design, the proposed twin-mode design requires 17% to 19p.c extra hardware resources, with threep.c to fivepercent period overhead. As compared to previous art on this, the proposed design out-performs them in terms of needed area, time-amount and throughput. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA - 2017 Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials - 2017
