A Multimode Area-Efficient SCL Polar Decoder - 2016 PROJECT TITLE : A Multimode Area-Efficient SCL Polar Decoder - 2016 ABSTRACT: Polar codes are of nice interest, since they're the primary provably capability-achieving forward error correction codes. To boost throughput and to cut back decoding latency of polar decoders, maximum probability (ML) decoding units are utilized by successive cancellation list (SCL) decoders and SC decoders. This paper proposes an approximate ML (AML) decoding unit for SCL decoders initial. In explicit, we have a tendency to investigate the distribution of frozen bits of polar codes designed for each the binary erasure and additive white Gaussian noise channels, and exploit the distribution to reduce the complexity of the AML decoding unit, improving the throughput-space potency of the SCL decoders. Furthermore, a multimode (MM) SCL decoder with variable list sizes and parallelism is proposed. If high throughput or little latency is required, the decoder decodes multiple received words in parallel with a tiny list size. However, if error performance is of higher priority, the MM-SCL decoder switches to a serial mode with a bigger list size. Thus, the MM-SCL decoder provides a versatile tradeoff between latency, throughput, and error performance at the expense of tiny overhead. Hardware implementation and synthesis results show that our polar decoders not solely have a better throughput-area potency however conjointly simply adapt to completely different Communication channels and applications. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Error Correction Codes Awgn Channels Binary Codes Maximum Likelihood Decoding Error Control Codes Maximum Likelihood (ML) Decoding Multimode (MM) Decoding Parallel Decoding Polar Codes Successive Cancellation List (SCL) Decoding Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes - 2016 Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016