Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials - 2017

PROJECT TITLE :

Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials - 2017

ABSTRACT:

In this paper, an efficient recursive formulation is advised for systolic implementation of canonical basis finite field multiplication over GF(2 m ) primarily based on irreducible AOP. We tend to have derived a recursive algorithm for the multiplication, and used that to design an everyday and localized bit-level dependence graph (DG) for systolic computation. The bit-level regular DG is converted into a fine-grained DG by node-splitting, and mapped that into a parallel systolic design. Unlike most of the present structures, it does not involve any international Communications for modular reduction. The proposed bit-parallel systolic structure has the identical cycle time as that of the most effective existing bit-parallel systolic structure [1], but involves significantly less variety of registers. The proposed bit-parallel design has a scalable latency of l + ?log two s? +one cycles which is significantly low compared with those of existing systolic designs. Moreover, the proposed time-multiplexed structure is intended specifically for scalability of throughput and hardware-complexity to meet the world-time trade-off in resource-constrained applications whereas maintaining or reducing the latency. The ASIC synthesis report shows that the proposed bit-parallel structures offers nearly 30p.c saving of space and nearly 38p.c saving of power consumption over the most effective of the existing AOP-based systolic finite field multiplier.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here