High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA - 2017


During this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A replacement segmented pipelined full-precision multiplier is employed to cut back the latency, and therefore the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid information dependency ensuing in a very drastic reduction in the quantity of clock cycles (CCs) needed. The proposed ECC design has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the simplest of our knowledge, our single- and 3-multiplier-based styles show the fastest performance to date compared with reported works individually. Our one-multiplier-based ECC processor also achieves the very best reported speed along with the most effective reported area-time performance on Virtex4 (five.thirty two µs at 210 MHz), on Virtex5 (4.91 µs at 228 MHz), and on the additional advanced Virtex7 (three.eighteen µs at 352 MHz). Finally, the proposed 3-multiplier-based ECC implementation is the primary work reporting the lowest variety of CCs and the fastest ECC processor style on FPGA (450 CCs to induce 2.83 µs on Virtex7).

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