Area-Efficient Architecture for Dual-Mode DoublePrecision Floating Point Division - 2017 PROJECT TITLE :Area-Efficient Architecture for Dual-Mode DoublePrecision Floating Point Division - 2017ABSTRACT:Floating point division may be a core arithmetic widely utilized in scientific and engineering applications. This paper proposed an design for double precision floating purpose division. This architecture is meant for dual-mode functionality, that will either compute on a combine of double precision operands or on 2 pairs of single precision operands in parallel. The architecture relies on the series expansion multiplicative methodology of mantissa computation. For this, a novel twin-mode Radix-4 Changed Booth multiplier is designed, which is employed iteratively within the architecture of twin-mode mantissa computation. Different key elements of floating point division flow (such as leading-one-detection, left/right dynamic shifters, rounding, etc.) are re-designed for the twin-mode operation. The proposed twin-mode design is synthesized using UMC 90 nm technology ASIC implementation. Two versions of proposed architecture are presented, one with single stage multiplier and another with 2 stage multiplier. Compared to a standalone double precision division architecture, the proposed dual-mode architecture needs seventeen% to 19% additional hardware resources, with 3percent to fivep.c amount overhead. Compared to previous art on this, the proposed architecture out-performs them in terms of required space, time-period and throughput. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects DLAU: A Scalable Deep Learning Accelerator Uniton FPGA - 2017 A Novel Data Format for Approximate Arithmetic Computing - 2017
