High-performance engineered gate transistor-based compact digital circuits - 2017


A unique methodology for coming up with and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate designed single devices within the pull-up (PU) and pull-down (PD) ways of a static CMOS gate instead of multiple transistors as utilized in standard CMOS implementations of circuits. Herein, 2 input NAND, NOR, and exclusive-OR (XOR) gates using the proposed gate engineering concept are designed and simulated. Engineered gate N-sort MOS and P-kind MOS are used for PD and pull-up circuits, respectively. Since solely 2 devices are used for an entire circuit: one in PU network and other in PD network; so, space and power of the proposed circuits get reduced considerably in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it will be extended to understand different combinational and sequential circuits simply.

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