High-performance engineered gate transistor-based compact digital circuits - 2017


A unique methodology for coming up with and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate designed single devices within the pull-up (PU) and pull-down (PD) ways of a static CMOS gate instead of multiple transistors as utilized in standard CMOS implementations of circuits. Herein, 2 input NAND, NOR, and exclusive-OR (XOR) gates using the proposed gate engineering concept are designed and simulated. Engineered gate N-sort MOS and P-kind MOS are used for PD and pull-up circuits, respectively. Since solely 2 devices are used for an entire circuit: one in PU network and other in PD network; so, space and power of the proposed circuits get reduced considerably in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it will be extended to understand different combinational and sequential circuits simply.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : A High-Performance Index for Real-Time Matrix Retrieval ABSTRACT: The representation of data has been significantly altered as a result of the "embedding" method, which is a fundamental part of machine learning.
PROJECT TITLE : High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators ABSTRACT: In a wide variety of applications, including image and video processing and machine learning, multiplication
PROJECT TITLE : Development of High-Performance ABSTRACT: The construction industry is increasingly using terms like "green buildings," "sustainable construction," and "high-performance buildings." A healthier interior environment
PROJECT TITLE :Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template - 2017ABSTRACT:We tend to propose a completely unique asynchronous logic (async) quasi-delay-insensitive (QDI)
PROJECT TITLE : A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016 ABSTRACT: Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry