Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops - 2017 PROJECT TITLE :Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops - 2017ABSTRACT:With technology down scaling, static power has become one in every of the most important challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements could be a promising resolution to handle this challenge. Recently, many NV shadow flip-flop architectures have been introduced in that magnetic tunnel junction (MTJ) cells are used as backup storing components. Because of the rising fabrication processes of magnetic layers, MTJs are a lot of prone to manufacturing defects than their CMOS counterparts. Moreover, in contrast to memory arrays which will effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are additional troublesome to repair. Thus, without effective defect and fault tolerance for NV flip-flops, the producing yield will be affected severely. In this paper, we tend to propose a fault-tolerant NV latch (FTNV-L) style, in that many MTJ cells are arranged in such a manner that it's resilient to numerous MTJ faults. The simulation results show that our proposed FTNV-L will effectively tolerate all single MTJ faults with a considerably lower overhead than ancient approaches. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI HSPICE MTech Projects Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits - 2017 High-performance engineered gate transistor-based compact digital circuits - 2017
