Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template - 2017


We tend to propose a completely unique asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high operational robustness, high speed, and low power dissipation. There are 5 key features of our proposed SAHB. Initial, the SAHB cell embodies the async QDI 4-phase (4f) signaling protocol to accommodate process-voltage-temperature variations. Second, the sense amplifier (SA) block in SAHB cells embodies a cross-coupled latch with a positive feedback mechanism to speed up the output analysis. Third, the analysis block in the SAHB includes each nMOS pull-up and pull-down networks with minimum transistor sizing to reduce the parasitic capacitance. Fourth, both the analysis block and SA block are tightly coupled to scale back redundant internal switching nodes. Fifth, the SAHB cell is meant in CMOS static logic and hence applicable for full-range dynamic voltage scaling operation for V DD ranging from nominal voltage (1 V) to subthreshold voltage (~zero.3 V). When six library cells embodying our proposed SAHB are compared with those embodying the traditional async QDI precharged [*fr1]-buffer (PCHB) approach, the proposed SAHB cells collectively feature simultaneous -.64p.c lower power, -.twenty onepercent faster, and ~sixpercent smaller IC area; the PCHB cell is inappropriate for subthreshold operation. A prototype sixty four-bit Kogge-Stone pipeline adder based mostly on the SAHB approach (at 65 nm CMOS) is designed. For a one-GHz throughput and at nominal VDD, the planning based mostly on the SAHB approach simultaneously features -.56p.c lower energy and -.twenty fourp.c lower transistor count advantages than its PCHB counterpart. When benchmarked against the ever-present synchronous logic counterpart, our SAHB dissipates -.39percent lower energy at the 1-GHz throughput.

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