High Performance Ternary Adder using CNTFET - 2017


Ternary logic may be a promising alternative to the conventional binary logic in VLSI style because it provides the benefits of reduced interconnects, higher operating speeds, and smaller chip area. This paper presents a pair of circuits for implementing a ternary half adder using carbon nanotube field-impact transistors. The proposed designs mix both futuristic ternary and conventional binary logic design approach. One in all the proposed circuits for ternary to binary decoder simplifies additional circuit implementation and provides glorious delay and power blessings in knowledge path circuit like adder. These circuits are extensively simulated using HSPICE to obtain power, delay, and power delay product. The circuit performances are compared with different styles reported in recent literature. One in every of the proposed ternary adders has been demonstrated power, power delay product improvement up to sixty threep.c and 66% respectively, with lesser transistor count. Thus, the utilization of those [*fr1] adders in complex arithmetic circuits will be advantageous.

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