PROJECT TITLE :
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016
Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in vital saving of computation. However, transpose kind configuration will circuitously support the block processing not like direct-form configuration. In this paper, we explore the likelihood of realization of block FIR filter in transpose type configuration for area-delay economical realization of enormous order FIR filters for each mounted and reconfigurable applications. Based mostly on an in depth computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose kind FIR filter. We tend to have derived a general multiplier-primarily based architecture for the proposed transpose kind block filter for reconfigurable applications. A low-complexity design using the MCM scheme is additionally presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less space-delay product (ADP) and fewer energy per sample (EPS) than the existing block implementation of direct-kind structure for medium or massive filter lengths, whereas for the short-length filters, the block implementation of direct-type FIR structure has less ADP and less EPS than the proposed structure. Application-specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length sixty four involves 42p.c less ADP and 40% less EPS than the simplest accessible FIR filter structure proposed for reconfigurable applications. For the identical filter length and the identical block size, the proposed structure involves thirteenpercent less ADP and twelve.eightp.c less EPS than that of the present direct-form block FIR structure.
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