High-Performance Approximate and Accurate Multipliers for Hardware Accelerators Based on FPGA

PROJECT TITLE :

High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators

ABSTRACT:

In a wide variety of applications, including image and video processing and Machine Learning, multiplication is one of the arithmetic operations that is utilized the most frequently. Multipliers with a high level of performance can be obtained from FPGA vendors in the form of DSP blocks. These multipliers are not only limited in number and have fixed locations on FPGAs, but they can also cause additional routing delays and may be inefficient for smaller bit-width multiplications. On FPGAs, these multipliers have fixed locations. Because of this, FPGA vendors additionally supply optimized soft IP cores for multiplication applications. However, in this piece of work, we argue that these soft multiplier IP cores for FPGAs still require improved designs in order to provide high-performance while using resources as efficiently as possible. In order to achieve this goal, we present generic area-optimized, low-latency accurate, and approximate softcore multiplier architectures. These architectures take advantage of the underlying architectural features of FPGAs, specifically lookup table (LUT) structures and fast-carry chains, in order to reduce the overall critical path delay (CPD) and resource utilization of multipliers. When compared to the Xilinx multiplier LogiCORE IP, our proposed unsigned and signed accurate architecture offers a reduction in LUT utilization that is up to 25% and 53% lower, respectively, depending on the size of the multiplier. In addition, with our unsigned approximate multiplier architectures, it is possible to achieve a reduction of up to 51% in the CPD while suffering only a negligible loss in output accuracy in comparison to the LogiCORE IP. This is made possible by the fact that our architectures are unsigned. As an illustration, we have implemented the proposed multiplier architecture in accelerators that are used in image and video applications, and we have evaluated these accelerators for improvements in both area and performance. Our library of exact and approximate multipliers is open source and can be downloaded from the internet at https://cfaed.tu-dresden.de/pd-downloads. Its purpose is to encourage additional research and development in this field, make it easier to reproduce research, and open up a new line of inquiry for the FPGA community.

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