PROJECT TITLE :
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design - 2016
Emerging nonvolatile recollections (NVMs), such as MRAM, PRAM, and RRAM, are widely investigated to replace SRAM because the configuration bits in field-programmable gate arrays (FPGAs) for top security and instant power ON. But, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This temporary introduces a coffee-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to beat the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to scale back the ability and space without impairing the reliability. Matched reference path is proposed to scale back the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, thirty eightp.c reduction in power, and also the tolerance of variations of 2.five× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs.
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