PROJECT TITLE :
A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System - 2016
A mounted-purpose squaring algorithm is formulated and implemented based mostly on an approach that allows any range of bits to be computed in every iterative step. The first contribution this new approach offers is the flexibility for a designer to change the world × latency product through the choice of a different radix or range of bits per subword to be processed in each iterative step. When the number of subword bits is increased, latency is reduced since fewer iterations are required whereas the realm is increased because of the larger subcircuit for squaring every subword. Alternatively, selecting a smaller subword or radix decreases space at the expense of skyrocketing latency since a lot of iterations are needed. The subword size can range from one bit yielding a touch-serial squarer requiring N iterations for an N-bit operand or “squarand,” to using the whole squarand ensuing in an exceedingly totally parallel squarer requiring no iterations. As a result of each m-bit subword will be considered a single digit in a very number system with radix 2m, the squarer presented here will be thought-about a multiple-valued logic (MVL) digit-serial design. This methodology allows for technologies primarily based on any radix of 2 or greater for use, including emerging technologies, thus yielding a true multiple-valued logic squaring circuit. The algorithm is derived through the generalization of a Vedic technique where any arbitrary integer-valued radix is used. Prototype hardware implementations using each a normal cell ASIC and FPGA technologies are developed. The prototype circuits are analyzed in terms of needed resources and throughput characteristics and compared to a well-known previous art squaring circuit.
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