Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems - 2016


The potency of the reconfiguration method in fashionable field-programmable gate arrays (FPGAs) will improve drastically if an on-chip configuration memory is included in the system, as a result of it will reduce both the reconfiguration latency and its energy consumption. However, the FPGA on-chip memory resources are terribly limited. Thus, it's terribly vital to manage them effectively in order to improve the reconfiguration process as much as possible, even when the size of the on-chip configuration memory is little. This paper presents a hardware implementation of an on-chip configuration memory controller that efficiently manages run-time reconfigurations. So as to optimize the utilization of the on-chip memory, this controller includes support to house configurations that have been divided into blocks of customizable size. When a reconfiguration should be meted out, our controller provides the blocks stored on-chip and appearance for the remaining blocks by accessing to the off-chip configuration memory. Moreover, it dynamically decides that blocks must be stored on-chip. To this finish, the designed controller implements a easy but efficient technique that allows maximizing the advantages of the on-chip reminiscences. Experimental results will demonstrate that its implementation price is very affordable and that it introduces negligible run-time management overheads.

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