PROJECT TITLE :
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing - 2016
The flexibility and programmability of an application-specific instruction-set processor (ASIP) come at the expense of reduced space and energy potency compared to application-specific integrated circuit (ASIC) solutions. Nevertheless, ASIPs are desirable for versatile application domains like wireless communications and software defined radio (SDR). Usually, ASIP designers scale back the ASIC-ASIP potency gap by increasingly advanced architectures with decreasing flexibility and usability. This paper takes the opposite approach and presents concepts for a highly economical, light-weight SDR ASIP. Efficiency enablers embody straightforward but effective measures sort of a rigorously chosen instruction set, optimized information access techniques for efficient utilization of practical units, and the use of flexible floating-point arithmetic with runtime-adaptive numerical precision. We tend to gift a conceptual processor core to show the impact of those measures and discuss its potential and limitations compared to tailored ASIC solutions. For demonstration, we opt for the sector of linear multiple-input multiple-output (MIMO) detection. We present synthesis results for many design versions in 90 nm CMOS technology and also the corresponding energy benchmarks. Additionally, we have a tendency to show post-layout results for a specific design to demonstrate the feasibility of our concept.
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