MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016


During this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the primary style, a regular redundant carry-save MAC unit is intended using well known carry-save techniques. In the second style, a hybrid design is proposed to exploit quick carry chains of the FPGA together with double carry-save output encoding. The proposed theme exploits quick-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders aren't merged and also the results are kept in double carry-save format where extra redundancy reduces important path delay. Designed MAC units have 16×16-bit multiplier with forty-digit accumulate output for recursive multiply-add operations. The styles are synthesized on AlteraTM Stratix III FPGAs and give superior performance compared to traditional pipelined carry-propagate multiply-accumulate units. The fusion within the arithmetic structure provides best performance compared to standard pipelined multiplier based structures, exhausting multiplier based MAC units, and carry free redundant arithmetic primarily based MAC structures furthermore.

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