PROJECT TITLE :
Logic Synthesis in Reversible PLA - 2016
Reversible logic are motivated by thought of zero-energy computation. Re-configurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we have a tendency to propose a style algorithm for a PLA (Programmable Logic Array) with a newly designed low cost 3 × three reversible NMG (New Mux Gate) circuit for implementing multi-output ESOP (Exclusive-OR Sum of Product) functions. Additionally, we tend to propose a heuristic to sort and to comprehend the merchandise terms of ESOP functions in order to share the interior sub-product to cut back the amount of gates within the proposed circuit. The proposed algorithms make the planning economical with improvement 9.05% in number of gates, 25.fivep.c in garbage count and fourteen.fivep.c quantum price metric than existing techniques averagely. Performance is also analyzed by using MCNC benchmark circuits.
Did you like this research project?
To get this research project Guidelines, Training and Code... Click Here