Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures

PROJECT TITLE :

Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures

ABSTRACT:

Network-on-Chips (NoCs) are quickly changing into the standard Communication paradigm for the growing number of cores on the chip. While NoCs will deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and Communication channels that facilitate inter-core Communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and can result in a important increase in faults (both permanent and transient) and hardware failures. In this paper, we tend to propose QORE—a fault tolerant NoC design with Multi-Function Channel (MFC) buffers. The utilization of MFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by permitting the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, MFC buffers cut back router power and improve performance by eliminating in-router buffering. We have a tendency to utilize a Machine Learning technique in our link controllers to predict the direction of traffic flow in order to more efficiently reverse links. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by one.3 and throughput by two.3 compared to state-of-the art fault tolerant NoCs styles such as Ariadne and Vicis. Moreover, using Synopsys Style Compiler, we have a tendency to also show that network power in QORE is reduced by twenty one percent with minimal control overhead.

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