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Computer Architecture Letters

Computer Architecture Letters focuses on the areas of uniprocessor and multiprocessors computer systems, computer architecture, micro architecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. There has been going a rigorous research work going on these concepts and attained a high-impact results in these areas. We provide the real time projects on these topics for the students of Mtech, PhD and researchers.

List of articles in category Computer Architecture Letters
No. Project Titles Abstract
1. A Traffic Load Balancing Framework for Software-Defined Radio Access Networks Powered by Hybrid Energy Sources Abstract
2. Recommender System and Web 2.0 Tools to Enhance a Blended Learning Model Abstract
3. DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors Abstract
4. How the Brain Formulates Memory: A Spatio-Temporal Model Research Frontier Abstract
5. Adaptive Cache and Concurrency Allocation on GPGPUs Abstract
6. Gender classification based on fuzzy clustering and principal component analysis Abstract
7. Parasitic-Aware Design of Integrated DC–DC Converters With Spiral Inductors Abstract
8. Green’s Function Using Schelkunoff Integrals for Horizontal Electric Dipoles Over an Imperfect Ground Plane Abstract
9. Understanding openness Abstract
10. A Hybrid Semi-Digital Transimpedance Amplifier With Noise Cancellation Technique for Nanopore-Based DNA Sequencing Abstract
11. A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory Abstract
12. Time-Aware VMFlow Placement, Routing, and Migration for Power Efficiency in Data Centers Abstract
13. Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers Abstract
14. Toward a Unified Characterization of Mapping Algorithms in Cloud and MPSoC Environments Using a Literature-Based Approach Abstract
15. RFFE: A Buffer Cache Management Algorithm for Flash-Memory-Based SSD to Improve Write Performance Abstract
16. Aging degree evaluation for paper-oil insulation using the recovery voltage method Abstract
17. Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck Abstract
18. Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures Abstract
19. Properties of the Energy Transport for Plane-Parallel Polychromatic Surface Gravity Waves in Waters of Arbitrary Depth Abstract
20. Global versus essential post-disaster re-provisioning in telecom mesh networks Abstract
21. Real time identification of coherent groups for controlled islanding based on graph theory Abstract
22. Automated Engine Calibration of Hybrid Electric Vehicles Abstract
23. Bi-anisotropic Metamaterials Effective Constitutive Parameters Extraction Using Oblique Incidence S-Parameters Method Abstract
24. A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding Abstract
25. Performance analysis of Bayesian coalition game-based energy-aware virtual machine migration in vehicular mobile cloud Abstract
26. Toward energy-efficient cloud computing: Prediction, consolidation, and overcommitment Abstract
27. Remained p-GaN effect to turn-off energy loss (Eoff) in p-GaN gate power devices Abstract
28. Improper Signaling for Symbol Error Rate Minimization in -User Interference Channel Abstract
29. Time-Division Multiplexing for Testing DVFS-Based SoCs Abstract
30. Reversible Color Spaces without Increased Bit Depth and Their Adaptive Selection Abstract
31. PHEVs Bidirectional Charging/Discharging and SoC Control for Microgrid Frequency Stabilization Using Multiple MPC Abstract
32. Exploring Data-Level Error Tolerance in High-Performance Solid-State Drives Abstract
33. Architecting Flash-based Solid-State Drive for High-performance I/O Virtualization Abstract
34. Soft Failures in Large Datacenters Abstract
35. An Overview of Static Pipelining Abstract
36. A Case for Hybrid Discrete-Continuous Architectures Abstract
37. Cache Impacts of Datatype Acceleration Abstract
38. A HW/SW Co-designed Programmable Functional Unit Abstract
39. Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs Abstract
40. A High-Level Power Model for MPSoC on FPGA Abstract
41. Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor Abstract
42. Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities Abstract
43. Fault-Tolerant Vertical Link Design for Effective 3D Stacking Abstract
44. Heterogeneity in “Homogeneous” Warehouse-Scale Computers: A Performance Opportunity Abstract
45. Multilevel Cache Modeling for Chip-Multiprocessor Systems Abstract
46. On Supporting Rapid Thermal Analysis Abstract
47. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks Abstract

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