Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck


Memory bottleneck has continually been a serious cause for limiting the performance of computer systems. While in the past latency was the main concern, these days, lack of bandwidth becomes a limiting factor likewise, as a result of exploiting additional parallelism with the growing number of cores per die, that intensifies the pressure on the memory bus. In such an setting, any extra traffic to memory, like the I/O traffic could lead to degradation of the overall performance of the system. This work introduces the concept of Peripheral Memory, a software controlled memory that resides within the I/O domain and will be used for offloading I/O traffic from CPU memory. The Peripheral Memory handles 'I/O exclusive knowledge', information originated and terminated at I/O domain, and that does not need any processing by the CPU. The paper analyses the impact of I/O traffic on the general performance of the present systems and demonstrates that in various applications, I/O exclusive data occupies major half of memory bandwidth, as a result, degrading CPU processing performance and increasing power. The paper considers four totally different implementations of the Peripheral Memory: pageable, pinned, non-coherent split-traffic and duplicate-on-access. Our full-system simulator indicates that non-coherent split traffic configuration is the foremost economical implementation, that can provide up to four times speedup in the I/O processing rate for typical I/O intensive applications. Yet, based mostly on Power model and measurements tools, the paper demonstrates that the Peripheral Memory in a server system can lead to reduction of tens of Watts in the system power consumption or ten-20 % of the system power budget.

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