Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching - 2016 PROJECT TITLE : Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching - 2016 ABSTRACT: Message-passing-based inference algorithms have immense importance in real-world applications. In this paper, error resiliency of a message passing primarily based Markov random field (MRF) stereo matching hardware is explored and enhanced through the application of statistical error compensation. Error resiliency is of particular interest for subnanometer and postsilicon devices. The inherent robustness of iteration-primarily based MRF inference algorithms is explored and shows that small errors are tolerable, whereas large errors degrade the performance considerably. Based on these error characteristics, algorithmic noise tolerance (ANT) has been applied at the arithmetic, iteration, and system levels. Introducing timing errors via voltage overscaling, at the arithmetic level, results show that the ANT-primarily based hardware can tolerate a blunder rate of 21.3%, with performance degradation of only three.5% at an overhead of ninety seven.4%, compared with a slip-up-free hardware with an energy savings of thirty-nine.7p.c. To reduce compensation complexity, iteration and system-level compensation was explored. Results show that, compared with arithmetic level, system-level compensation reduces overhead to fifty ninepercent, whereas maintaining stereo matching performance with solely two.fivepercent degradation with 16% extra power savings. These results are verified via FPGA emulation with timing errors induced inside the message passing unit via relaxed synthesis. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Field Programmable Gate Arrays Error Statistics Message Passing Energy Conservation Image Matching Iterative Methods Markov Processes Stereo Image Processing Tolerance Analysis Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division - 2016 Trigger-Centric Loop Mapping on CGRAs - 2016