PROJECT TITLE :
Architectural Support for Mitigating Row Hammering in DRAM Memories
DRAM scaling has been the prime driver of accelerating capacity of main memory systems. Unfortunately, lower technology nodes worsen the cell reliability because it increases the coupling between adjacent DRAM cells, thereby exacerbating different failure modes. This paper investigates the reliability drawback due to Row Hammering, whereby frequent activations of a given row will cause data loss for its neighboring rows. As DRAM scales to lower technology nodes, the edge for the amount of row activations that causes information loss for the neighboring rows reduces, creating Row Hammering a challenging drawback for future DRAM chips. To overcome Row Hammering, we propose two architectural solutions: Initial, Counter-Based Row Activation (CRA), which uses a counter with every row to count the number of row activations. If the count exceeds the row hammering threshold, a dummy activation is distributed to neighboring rows proactively to refresh the information. Second, Probabilistic Row Activation (PRA), that obviates storage overhead of tracking and merely allows the memory controller to proactively issue dummy activations to neighboring rows with a tiny chance for all memory access. Our evaluations show that these solutions are effective at mitigating Row hammering whereas causing negligible performance loss (<; 1 p.c).
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