Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors


This paper presents a lifetime reliability characterization of the many-core processors primarily based on a full-system simulation of integrated microarchitecture, power, thermal, and reliability models. Underneath normal operating conditions, our model and analysis reveal that the mean-time-to-failure of cores on the die show traditional distribution. From the processor-level perspective, the key insight is that reducing the variance of the distribution can improve lifetime reliability by avoiding early failures. Based mostly on this understanding, we gift two variance reduction techniques for proactive reliability management; i) proportional dynamic voltage-frequency scaling (DVFS) and ii) coordinated thread swapping. A major advantage of using variance reduction techniques is that the improvement of system lifetime reliability will be achieved without adding design margins or spare components.

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