A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems


As the number of cores on a chip will increase and key applications become even a lot of knowledge-intensive, memory systems in fashionable processors have to accommodate increasingly giant quantity of knowledge. In face of such challenges, information compression presents as a promising approach to extend effective memory system capacity and conjointly provide performance and energy blessings. This paper presents a survey of techniques for using compression in cache and main memory systems. It conjointly classifies the techniques based mostly on key parameters to spotlight their similarities and differences. It discusses compression in CPUs and GPUs, standard and non-volatile memory (NVM) systems, and 2D and 3D memory systems. We tend to hope that this survey will help the researchers in gaining insight into the potential role of compression approach in memory elements of future extreme-scale systems.

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