Architectural Protection of Application Privacy against Software and Physical Attacks in Untrusted Cloud Environment - 2018


In cloud computing, it is usually assumed that cloud vendors are trusted; the guest Operating System (OS) and also the Virtual Machine Monitor (VMM, additionally called Hypervisor) are secure. But, these assumptions don't seem to be continually true in follow and existing approaches cannot protect the information privacy of applications when none of these parties are trusted. We have a tendency to investigate how to deal with a robust threat model that is that the cloud vendors, the guest OS, or the VMM, or each of them are malicious or untrusted, and will launch attacks against privacy of trusted user applications. This model has relevancy as a result of applications may be tiny enough to be formally verified, while the guest OS and VMM are too complex to be formally verified. Specifically, we gift the design and analysis of an architectural solution that integrates a set of elements on-chip to shield the memory of trusted applications from potential software and hardware primarily based attacks from untrusted cloud providers, compromised guest OS, or malicious VMM. Full-system performance evaluation results show that the design solely incurs 9 % overhead on average, that is a little performance price that is got the substantial security gain.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems - 2016 ABSTRACT: The potency of the reconfiguration method in fashionable field-programmable gate arrays (FPGAs)
PROJECT TITLE :A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory SystemsABSTRACT:As the number of cores on a chip will increase and key applications become even a lot of knowledge-intensive, memory
PROJECT TITLE :Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core ProcessorsABSTRACT:This paper presents a lifetime reliability characterization of the many-core processors primarily based
PROJECT TITLE :Architectural Support for Mitigating Row Hammering in DRAM MemoriesABSTRACT:DRAM scaling has been the prime driver of accelerating capacity of main memory systems. Unfortunately, lower technology nodes worsen the
PROJECT TITLE :Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimationABSTRACT:Miniaturisation in fashionable microprocessors increases susceptibility to soft errors

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry