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IEEE ROOT Projects at MTech Projects feature the latest project topics with Abstract, Source Code, Thesis, Report, Documentation, Research Paper Writing, Presentation ppt, Video demo, and Expert guidance for BTech, MTech, BE, ME, MS and PhD students. We support engineering students and researchers across Hyderabad, Bengaluru, Chennai, Mumbai, Delhi, Pune, Kolkata, Ahmedabad, Kochi and other major cities in India, USA, UK.

Latest ROOT IEEE Project Titles [2026]

S.No Project Title Abstract
301 An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016 Abstract
302 CWFP: Novel Collective Write back and Fill Policy for LastLevel DRAM Cache - 2016 Abstract
303 High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver - 2016 Abstract
304 Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes - 2016 Abstract
305 A Multimode Area-Efficient SCL Polar Decoder - 2016 Abstract
306 Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 Abstract
307 A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction - 2016 Abstract
308 High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) - 2016 Abstract
309 A High Throughput List Decoder Architecturefor Polar Codes - 2016 Abstract
310 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016 Abstract
311 A New XOR-Free Approach for Implementation of Convolutional Encoder - 2016 Abstract
312 An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code - 2016 Abstract
313 A New CDMA Encoding/Decoding Method for on-Chip Communication Network - 2016 Abstract
314 High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols - 2016 Abstract
315 Digital Multiplierless Realization of Two-CoupledBiological Hindmarsh–Rose Neuron Model - 2016 Abstract
316 Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016 Abstract
317 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits - 2016 Abstract
318 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers - 2016 Abstract
319 Memory-Reduced Turbo Decoding ArchitectureUsing NII Metric Compression - 2016 Abstract
320 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers - 2016 Abstract

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