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IEEE ROOT Projects at MTech Projects feature the latest project topics with Abstract, Source Code, Thesis, Report, Documentation, Research Paper Writing, Presentation ppt, Video demo, and Expert guidance for BTech, MTech, BE, ME, MS and PhD students. We support engineering students and researchers across Hyderabad, Bengaluru, Chennai, Mumbai, Delhi, Pune, Kolkata, Ahmedabad, Kochi and other major cities in India, USA, UK.

Latest ROOT IEEE Project Titles [2026]

S.No Project Title Abstract
241 Wireless Energy Harvesting in a Cognitive Relay Network - 2016 Abstract
242 A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System - 2016 Abstract
243 An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016 Abstract
244 An Improved Signed Digit Representation Approach for Constant Vector Multiplication - 2016 Abstract
245 Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach - 2016 Abstract
246 Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design - 2016 Abstract
247 Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs - 2016 Abstract
248 Logic Synthesis in Reversible PLA - 2016 Abstract
249 MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016 Abstract
250 Multi Precision Arithmetic Adders - 2016 Abstract
251 Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit - 2016 Abstract
252 Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios - 2016 Abstract
253 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2016 Abstract
254 Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m) - 2016 Abstract
255 Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest - 2016 Abstract
256 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic - 2016 Abstract
257 A Modified Partial Product Generator for Redundant Binary Multipliers - 2016 Abstract
258 Arithmetic algorithms for extended precisionusing floating-point expansions - 2016 Abstract
259 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding - 2016 Abstract
260 Performance/Power Space Exploration for Binary64 Division Units - 2016 Abstract

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