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IEEE ROOT Projects at MTech Projects feature the latest project topics with Abstract, Source Code, Thesis, Report, Documentation, Research Paper Writing, Presentation ppt, Video demo, and Expert guidance for BTech, MTech, BE, ME, MS and PhD students. We support engineering students and researchers across Hyderabad, Bengaluru, Chennai, Mumbai, Delhi, Pune, Kolkata, Ahmedabad, Kochi and other major cities in India, USA, UK.

Latest ROOT IEEE Project Titles [2026]

S.No Project Title Abstract
281 Optimized Built-In Self-Repair for Multiple Memories - 2016 Abstract
282 A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm - 2016 Abstract
283 Network-on-Chip for Turbo Decoders - 2016 Abstract
284 Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation - 2016 Abstract
285 Speculative Look ahead for Energy-Efficient Microprocessors - 2016 Abstract
286 Efficient Synchronization for Distributed Embedded Multiprocessors - 2016 Abstract
287 NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices - 2016 Abstract
288 A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies - 2016 Abstract
289 Knowledge-Based Neural Network Model for FPGA Logical Architecture Development - 2016 Abstract
290 A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes - 2016 Abstract
291 A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing - 2016 Abstract
292 Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems - 2016 Abstract
293 Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division - 2016 Abstract
294 Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching - 2016 Abstract
295 Trigger-Centric Loop Mapping on CGRAs - 2016 Abstract
296 PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash - 2016 Abstract
297 Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures - 2016 Abstract
298 A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic - 2016 Abstract
299 An Efficient Decoder Architecture for Non-binary LDPC Codes with Extended Min-Sum Algorithm - 2016 Abstract
300 An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding - 2016 Abstract

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