PROJECT TITLE :

Register – Less NULL Conventional Logic - 2017

ABSTRACT:

NULL Convention Logic (NCL) may be a promising style paradigm for constructing low-power strong asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and people registers will account for up to thirty fivepercent of the overall power consumption of the NCL circuit. This transient presents the Register-Less NCL (RL-NCL) style paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the traditional NCL counterpart, the RL-NCL implementation of an eight-bit 5-stage pipelined Kogge-Stone adder will cut back power dissipation by 56.4%-72.5percent for the input data rate starting from 10 to 900 MHz. Moreover, the RL-NCL implementation will cut back the transistor count of the adder by forty nine.fivep.c.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE : A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register - 2016 ABSTRACT: This transient presents a quick-acquisition 11-bit all-digital
PROJECT TITLE : Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs - 2016 ABSTRACT: Scan flip -- flop insertion for aiding design for testability invitations additional hardware overhead,
PROJECT TITLE: TM-RF Aging-Aware Power-Efficient Register File Design for Modern Microprocessors - 2015 ABSTRACT: Modern microprocessors use register files (RFs) for performance enhancement and achieving instruction level parallelism
PROJECT TITLE :The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applicationsABSTRACT:Over the past decade, the successive approximation register (SAR) design has played
PROJECT TITLE :A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductorABSTRACT:A design of a 10-bit 27.8 kS/s zero.35 V ultra-low

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry