The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications


Over the past decade, the successive approximation register (SAR) design has played a significant role in advancing the state-of-the-art in analog-to-digital conversion. One in all the primary reasons for this can be that trendy SAR ADCs thrive on MOS switches and latches, which strongly benefit from technology scaling. Building on this observation, this text compares the strengths and limitations of SAR ADCs against those of competing topologies and comes and connected performance bounds. In this context, we have a tendency to also discuss application-specific issues, specifically for ultra-low power and ultra-high speed (time-interleaved) application scenarios.

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