PROJECT TITLE :
Probability-Driven Multibit Flip-Flop Integration With Clock Gating - 2017
Knowledge-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are 2 low-power style techniques that are usually treated separately. Combining these techniques into a single grouping algorithm and style flow enables any power savings. We study MBFF multiplicity and its synergy with FF data-to-clock toggling chances. A probabilistic model is implemented to maximise the expected energy savings by grouping FFs in increasing order of their information-to-clock toggling chances. We have a tendency to present a front-end design flow, guided by physical layout considerations for a 65-nm 32-bit MIPS and a twenty eight-nm industrial network processor. It is shown to attain the facility savings of twenty threep.c and 17%, respectively, compared with designs with ordinary FFs. Regarding [*fr1] of the savings was thanks to integrating the DDCG into the MBFFs.
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