PROJECT TITLE :
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register - 2016
This transient presents a quick-acquisition 11-bit all-digital delay-locked loop (ADDLL) employing a novel starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). It will effectively eliminate the harmonic lock and therefore the false lock. The achievable acquisition time is inside 17.five-23.five or 17.five-thirty two.5 clock cycles when the ADDLL works at the low or high clock rate, respectively. The digital-controlled delay line and also the SBP-SAR of the ADDLL chip are synthesized using Taiwan Semiconductor Manufacturing Company's (TSMC's) zero.eighteen-µm CMOS cell library. The proposed ADDLL will operate at a clock frequency from sixty MHz to 1.1 GHz.
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