Reconfigurable Constant Multiplication for FPGAs - 2017 PROJECT TITLE :Reconfigurable Constant Multiplication for FPGAs - 2017ABSTRACT:This paper introduces a replacement heuristic to get pipelined run-time reconfigurable constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to the optimum. It is primarily based on an optimal algorithm that fuses already optimized pipelined constant multipliers generated by an existing heuristic referred to as reduced pipelined adder graph (RPAG). Switching between different single or multiple constant outputs is realized by the insertion of multiplexers. The heuristic searches for a resolution that ends up in minimal multiplexer overhead. Using the proposed heuristic reduces the run-time of the fusion method, that raises the usability and application domain of the proposed methodology of run-time reconfiguration. An extensive evaluation of the proposed method confirms a ninepercent-twenty six% FPGA resource reduction on average compared to previous work. For reconfigurable multiple constant multiplication, resource savings of up to 75percent can be shown compared to a normal generic lookup table based mostly multiplier. Two low level optimizations are presented, which further scale back resource consumption and are included into an automatic VHDL code generation based mostly on the FloPoCo library. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs - 2017 DLAU: A Scalable Deep Learning Accelerator Uniton FPGA - 2017
