DLAU: A Scalable Deep Learning Accelerator Uniton FPGA - 2017


Because the emerging field of machine learning, deep learning shows excellent ability in solving advanced learning problems. However, the dimensions of the networks becomes increasingly large scale because of the demands of the practical applications, that poses important challenge to construct a high performance implementations of deep learning neural networks. In order to improve the performance also to keep up the low power cost, in this paper we design DLAU, that may be a scalable accelerator architecture for massive-scale deep learning networks using FPGA as the hardware prototype. The DLAU accelerator employs 3 pipelined processing units to improve the throughput and utilizes tile techniques to explore locality for deep learning applications. Experimental results on the state-of-the-art Xilinx FPGA board demonstrate that the DLAU accelerator is able to realize up to 36.1x speedup comparing to the Intel Core2 processors, with the ability consumption at 234mW.

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